In Modelsim, you use the -sdfxxx command to tell it what kind of timing simulation you want. The simulation can also be run in conjunction with a timing netlist or. You can use that to check that the top-level waveforms look identical. The post-synthesis simulation can be run without timing delays. Some of the 'secret sauce' of the FPGA will still be hidden from you using basic components, that Altera calls atoms (that's why you need a different set of libraries for netlist simulation in Modelsim-SE, Modelsim-ASE has them precompiled). If you look at that netlist, you'll see its been 'flattened' so its just one huge file. In a post-synthesis simulation, the simulator compiles the netlist generated by the synthesis tool (the Quartus. In an RTL simulation, the simulator compiles the VHDL in your components and any simulation models, instantiates that in your testbench and runs. Could you explain to me what is difference between RTL functional simulation and post-synthesis simulation?
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